1. Field of the Invention
This invention relates to the field of semiconductor processing and, more particularly, to an integrated circuit and method of making same, wherein a transistor is fabricated a spaced distance above another transistor to produce a higher density of active devices on a wafer.
2. Description of Relevant Art
Fabrication of a metal-oxide-semiconductor ("MOS") transistor is well-known. Fabrication typically begins by introducing n-type or p-type impurities into a single-crystal silicon substrate. The active regions of the substrate (where the transistors will be formed) are then isolated from each other using isolation structures. In modem fabrication technologies, the isolation structures may comprise shallow trenches in the substrate filled with a dielectric such as oxide which acts as an insulator. Isolation structures may alternatively comprise, for example, locally oxidized silicon ("LOCOS") structures. A gate dielectric is then formed by oxidizing the silicon substrate. Oxidation is generally performed in a thermal oxidation furnace or, alternatively, in a rapid-thermal-anneal ("RTA") apparatus. A gate conductor is then patterned using a photolithography/etch process from a layer of polycrystalline silicon ("polysilicon") deposited upon the gate dielectric. The photolithography process allows selective removal of a photoresist film deposited entirely across the polysilicon. The portion of the photoresist film that is exposed can, according to one embodiment, be polymerized, and that which is not exposed removed during the "develop" stage of the lithography process. The regions that are non-polymerized form a mask for a subsequent etch during which portions of the polysilicon layer that are not masked by the photoresist pattern are removed. After the etch process, the patterned photoresist layer is stripped away.
In the submicron range, it is very critical to produce gate conductors with substantially vertical sidewalls. The width of the gate conductor determines the channel length of the device, which is very critical to the performance of the device. This is insignificant for devices with longer channel lengths but more critical for submicron devices. It is difficult to produce a polysilicon gate conductor with substantially vertical sidewalls. Sloped sidewalls are common resulting in longer channel lengths.
The polysilicon is typically rendered conductive with the introduction of ions from an implanter or a diffusion furnace. Subsequently, source and drain regions are doped with a high-dose n-type or p-type dopant. If the source and drain regions are doped n-type, the transistor is referred to as NMOS, and if the source and drain regions are doped p-type, the transistor is referred to as PMOS. A channel region between the source and the drain is protected from the implant species by the pre-existing gate conductor. When an appropriate bias is applied to the gate of an enhancement-mode transistor, a conductive channel between the source and drain is induced and the transistor turns on.
Because of the increased desire to build faster and more complex integrated circuits, it has become necessary to form relatively small, closely spaced transistors within a single integrated circuit. Unfortunately, since transistors are generally formed within the silicon-based substrate of an integrated circuit, the number of transistors per integrated circuit is limited by the available lateral area of the substrate. Moreover, transistors cannot employ the same portion of a substrate, and increasing the area occupied by the substrate is an impractical solution to this problem. Thus, packing density of an integrated circuit is somewhat sacrificed by the common practice of forming transistors exclusively within a substrate having a limited amount of area. Having more densely packed transistors would result in an increase in the number of devices, such as central processing units, memory chips, etc., formed on each wafer.
It would therefore be desirable that a semiconductor fabrication process be developed for the formation of more densely packed transistors. Such a process would lead to an increase in circuit speed as well as an increase in circuit complexity.